Dark current and lag reduction

ABSTRACT

The claimed subject matter provides systems and/or methods that facilitate reducing dark current and lag in a CMOS imaging System-on-Chip (iSoC) sensor. For instance, a vertical output driver can output a signal upon a node connected to gates of reset transistors and/or gates of transfer transistors of pixels in the pixel array while operating in rolling shutter mode and/or global shutter mode. Further, a pre-charger can transition a voltage of the node to a first voltage level. Moreover, a booster can further adjust the voltage of the node from the first voltage level to a second voltage level. The booster can have variable drive capability that enables varying operation thereof according to at least one degree of freedom (e.g., speed of the booster proceeding to the second voltage level, frequency of yielding charge to the node, the second voltage level, or timing of the booster and the pre-charger, . . . ).

BACKGROUND

Recent technological advances have led to complementarymetal-oxide-semiconductor (CMOS) sensor imagers being leveraged bycameras, video systems, and the like. CMOS sensor imagers can include anintegrated circuit with an array of pixel sensors, each of which cancomprise a photodetector. Moreover, a CMOS sensor imager can beincorporated into a System-on-Chip (SoC). As such, the SoC can integratevarious components (e.g., analog, digital, . . . ) associated withimaging into a common integrated circuit. For instance, the SoC caninclude a microprocessor, microcontroller, or digital signal processor(DSP) core, memory, analog interfaces (e.g., analog to digitalconverters, digital to analog converters), and so forth.

Visible imaging systems implemented using CMOS imaging sensors canreduce costs, power consumption, and noise while improving resolution.For instance, cameras can use CMOS imaging System-on-Chip (iSoC) sensorsthat efficiently marry low-noise image detection and signal processingwith multiple supporting blocks that can provide timing control, clockdrivers, reference voltages, analog to digital conversion, digital toanalog conversion and key signal processing elements. High-performancevideo cameras can thereby be assembled using a single CMOS integratedcircuit supported by few components including a lens and a battery, forinstance. Accordingly, by leveraging iSoC sensors, camera size can bedecreased and battery life can be increased. Also, dual-use cameras haveemerged that can employ iSoC sensors to alternately producehigh-resolution still images or high definition (HD) video.

A CMOS imaging sensor can include an array of pixel cells, where eachpixel cell in the array can include a photodetector (e.g., photogate,photoconductor, photodiode, . . . ) that overlays a substrate foryielding a photo-generated charge. A readout circuit can be provided foreach pixel cell and can include at least a source follower transistor.The pixel cell can also include a floating diffusion region connected toa gate of the source follower transistor. Accordingly, charge generatedby the photodetector can be sent to the floating diffusion region.Further, the imaging sensor can include a transistor for transferringcharge from the photodetector to the floating diffusion region andanother transistor for resetting the floating diffusion region to apredetermined charge level prior to charge transference. Moreover, threesignals can be provided to each pixel cell in the pixel array: atransfer (TX) signal, a reset signal, and a select signal.

The array of pixels cell can operate in a variety of modes. Forinstance, rolling shutter operation can be utilized to readout a singlerow of pixels from the pixel array at a particular time. According toanother example, a global shutter can be employed to readout all rows(or substantially all rows) of pixels from the array at a given time. Toenable readout from the array, conventional techniques oftentimes use abooster to boost signals provided to each pixel in the array; moreparticularly, the booster can be utilized to increase voltages aboveVdd, which is a positive supply voltage, and/or decrease voltages belowGround for transfer signals and/or reset signals provided to pixels inthe array. However, commonly employed boosters can lack sufficient speedfor reading out pixels from the array when operating in rolling shuttermode or global shutter mode. Conventional boosters can also introducerow-to-row variation of boosted voltage levels. Moreover, typicalboosters oftentimes are unable to drive large loads that are commonlyencountered when operating in global shutter mode.

SUMMARY

The following presents a simplified summary in order to provide a basicunderstanding of some aspects described herein. This summary is not anextensive overview of the claimed subject matter. It is intended toneither identify key or critical elements of the claimed subject matternor delineate the scope thereof. Its sole purpose is to present someconcepts in a simplified form as a prelude to the more detaileddescription that is presented later.

The claimed subject matter relates to systems and/or methods thatfacilitate reducing dark current and lag in a CMOS imagingSystem-on-Chip (iSoC) sensor. For instance, a vertical output driver canoutput a signal upon a node connected to gates of reset transistorsand/or gates of transfer transistors of pixels in the pixel array whileoperating in rolling shutter mode and/or global shutter mode. Further, apre-charger can transition a voltage of the node to a first voltagelevel. Moreover, a booster can further adjust the voltage of the nodefrom the first voltage level to a second voltage level. The booster canhave variable drive capability that enables varying operation thereofaccording to at least one degree of freedom (e.g., speed of the boosterproceeding to the second voltage level, frequency of yielding charge tothe node, the second voltage level, or timing of the booster and thepre-charger, . . . ).

According to various aspects, the booster can include a plurality ofcomponents. For instance, the booster can include a voltage-controlledoscillator (VCO) that outputs clock signals at a frequency set by aninputted current. Further, the booster can comprise a set of chargepumps that can be parallel to each other. A subset of the set of chargepumps can be activated via an enable bus to generate charge outputtedupon a boosted node for each of the clock signals. Moreover, the boostercan include a resistor divider that generates a feedback voltage as afunction of a voltage of the boosted node. Additionally, the booster cancomprise a comparator that compares the feedback voltage to a referencevoltage (e.g., the reference voltage can be adjustable to tailor atarget voltage of the boosted node). The booster can also include an ANDgate that enables or inhibits the VCO at a given time based upon outputof the comparator and a boost enable signal.

The following description and the annexed drawings set forth in detailcertain illustrative aspects of the claimed subject matter. Theseaspects are indicative, however, of but a few of the various ways inwhich the principles of such matter may be employed and the claimedsubject matter is intended to include all such aspects and theirequivalents. Other advantages and novel features will become apparentfrom the following detailed description when considered in conjunctionwith the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example system that boosts voltage(s) upon bus(es)provided to pixels in a CMOS sensor imager.

FIG. 2 illustrates an example CMOS imager pixel cell that can beincluded in a pixel array.

FIG. 3 illustrates an example system that positively and/or negativelyboosts a signal for utilization with a CMOS sensor imager.

FIG. 4 illustrates an example system that generates output signalsprovided to gates of transfer transistors and/or reset transistors ofpixels in a pixel array of a CMOS sensor imager.

FIG. 5 illustrates example diagrams depicting body connections ofpre-charge devices in accordance with various aspects of the claimedsubject matter.

FIG. 6 illustrates an example system that controls voltage boosting in aCMOS sensor imager.

FIG. 7 illustrates an example methodology that facilitates reducing lagand dark current in a CMOS sensor imager.

FIG. 8 illustrates an example methodology that facilitates controlling abooster utilized in connection with a CMOS sensor imager.

FIG. 9 illustrates an example networking environment, wherein the novelaspects of the claimed subject matter can be employed.

FIG. 10 illustrates an example operating environment that can beemployed in accordance with the claimed subject matter.

DETAILED DESCRIPTION

The claimed subject matter is described with reference to the drawings,wherein like reference numerals are used to refer to like elementsthroughout. In the following description, for purposes of explanation,numerous specific details are set forth in order to provide a thoroughunderstanding of the subject innovation. It may be evident, however,that the claimed subject matter may be practiced without these specificdetails. In other instances, well-known structures and devices are shownin block diagram form in order to facilitate describing the subjectinnovation.

As utilized herein, terms “component,” “system,” and the like areintended to refer to a computer-related entity, either hardware,software (e.g., in execution), and/or firmware. For example, a componentcan be a process running on a processor, a processor, an object, anexecutable, a program, and/or a computer. By way of illustration, bothan application running on a server and the server can be a component.One or more components can reside within a process and a component canbe localized on one computer and/or distributed between two or morecomputers.

Furthermore, the claimed subject matter may be implemented as a method,apparatus, or article of manufacture using standard programming and/orengineering techniques to produce software, firmware, hardware, or anycombination thereof to control a computer to implement the disclosedsubject matter. The term “article of manufacture” as used herein isintended to encompass a computer program accessible from anycomputer-readable device, carrier, or media. For example, computerreadable media can include but are not limited to magnetic storagedevices (e.g., hard disk, floppy disk, magnetic strips, . . . ), opticaldisks (e.g., compact disk (CD), digital versatile disk (DVD), . . . ),smart cards, and flash memory devices (e.g., card, stick, key drive, . .. ). Additionally it should be appreciated that a carrier wave can beemployed to carry computer-readable electronic data such as those usedin transmitting and receiving electronic mail or in accessing a networksuch as the Internet or a local area network (LAN). Of course, thoseskilled in the art will recognize many modifications may be made to thisconfiguration without departing from the scope or spirit of the claimedsubject matter. Moreover, the word “exemplary” is used herein to meanserving as an example, instance, or illustration. Any aspect or designdescribed herein as “exemplary” is not necessarily to be construed aspreferred or advantageous over other aspects or designs.

With reference to FIG. 1, illustrated is a system 100 that boostsvoltage(s) upon bus(es) provided to pixels in a CMOS sensor imager. Thesystem 100 can be associated with a CMOS sensor imager utilized inconnection with a camcorder, digital camera, microscope, video system,and/or the like. The system 100 comprises a pixel array 102 that caninclude M rows and N columns of pixel cells, where M and N can be anyintegers. Each pixel in the pixel array 102 can comprise a photodetector(e.g., photogate, photoconductor, photodiode, . . . ). Further, eachpixel in the pixel array 102 can be utilized to detect a particularcolor of light; thus, a subset of the pixels in the pixel array 102 canoperate in response to red light (R pixels), a disparate subset of thepixels can operate based upon blue light (B pixels) and a further subsetof the pixels can operate as a function of green light (G pixels). Othercolor filter patterns are also possible.

An image focused on the pixel array 102 can cause the pixels to convertincident light into electrical energy. Signals obtained by the pixelarray 102 can be processed on a column by column basis; thus, aparticular row of pixels from the pixel array 102 can be selected to beread. The system 100 can further include a plurality of read buses 104that can transfer the contents from the pixels in the pixel array 102 inthe selected row. According to an illustration, the system 100 caninclude N read buses 104, where each read bus 104 can be associated witha respective column of the pixel array 102. By way of further example,pixels in the pixel array 102 can share read buses 104, and thus, thesystem 100 can include fewer than N read buses 104.

Each read bus 104 can carry content (e.g., sampled signals) from thepixels to a respective column buffer (CB) 106. The system 100 caninclude N column buffers 106 or fewer, for instance. The column buffers106 can amplify (e.g., condition) the signals from the pixels. Further,each column buffer 106 can enable low noise readout and can conditionthe signal from a pixel positioned at one of the rows in the column (orcolumns) corresponding to the column buffer 106.

After processing by the column buffers 106, outputted values from eachof the column buffers 106 can be retained. Moreover, each of the columnbuffers 106 can be associated with respective circuitry such as, forinstance, a respective capacitor 108 and switch 110. Such circuitry cansample and hold outputted values from the corresponding column buffers106. For example, the capacitors 108 can be loaded with the outputtedvalues from the corresponding column buffers 106. Further, the switches110 can be closed one at a time to allow for connecting to a bus 112;thus, the voltages generated by the column buffers 106 can bemultiplexed over the bus 112. The bus 112 can enable communicating eachof the outputted values from the respective column buffers 106 to ananalog to digital converter (ADC) 114. The ADC 114 can digitize thesampled signal to yield a digital signal. The digital signal canthereafter be provided to disparate component(s) (not shown) for furtherprocessing, manipulation, storage, display, and so forth.

The system 100 can also include a vertical output driver 116, apre-charger 118 and a booster 120. Although not shown, it is alsocontemplated that each row of the pixel array 102 or each signal (e.g.,each signal to be boosted and thereafter communicated to pixels, . . . )in each row of the pixel array 102 can be associated with a respectivevertical output driver, pre-charger and/or booster, each of which can besubstantially similar to the vertical output driver 116, the pre-charger118, and the booster 120 as described herein.

The vertical output driver 116 can be an output stage of a verticalscanner (not shown). The vertical output driver 116 can outputvoltage(s) (e.g., signal(s)) to gates of various transistors of pixelsincluded the pixel array 102. By way of illustration, the verticaloutput driver 116 can provide an output voltage to one or more buses(e.g., one or more nodes, . . . ) that can connect to gates of resettransistors, gates of transfer transistors, and/or gates of selecttransistors and other signals that may be present in other kinds ofpixel architectures; thus, the vertical output driver 116 can generate areset signal that is provided to reset transistors of pixels, a transfersignal that is provided to transfer transistors of pixels, and/or aselect signal that is provided to select transistors of pixels. Forinstance, the vertical output driver 116 can output a high voltage level(e.g., Vdd) or a low voltage level (e.g., Ground) to the one or morebuses. Moreover, the signals provided to the pixels of the pixel array102 by the vertical output driver 116 can be boosted above Vdd and/orboosted below Ground; for instance, the reset signal(s) and the transfersignal(s) can be boosted, while the select signal(s) may not need to beboosted.

The pre-charger 118 can pre-charge the signal to be outputted upon a busby the vertical output driver 116; by pre-charging, the signal can betransitioned to a high voltage level or a low voltage level. Moreparticularly, the pre-charger 118 can pre-charge the signals for theentire pixel array 102 or a portion thereof. For instance, thepre-charger 118 can pre-charge all rows of the pixel array 102 whenoperating in a global shutter mode. According to another example, thepre-charger 118 can pre-charge a subset of rows out of the M rows of thepixel array 102 at a given time (e.g., one row, two rows, etc. at aparticular time) while in rolling shutter mode. The pre-charger 118 canbe tied to supply voltages, and thus, the pre-charger 118 can provide alarge amount of current to the bus being pre-charged; providing thislarge amount of current enables the output provided to the gates of thereset transistors and/or the transfer transistors to quickly transitionbetween states (e.g., quickly switch from the high voltage level to thelow voltage level and/or quickly switch from the low voltage level tothe high voltage level, where the high voltage level can be Vdd and thelow voltage level can be Ground, . . . ). By way of furtherillustration, the output provided to the gates of the reset transistorsand/or the gates of the transfer transistors can quickly transition froma boosted voltage level above the high voltage level to the low voltagelevel and/or from a boosted voltage level below the low voltage level tothe high voltage level. Although shown as utilizing a common pre-charger118 for positive and negative boosting, it is to be appreciated thatseparate pre-chargers can be employed for positive boosting and negativeboosting. Further, the pre-charger 118 can be connected to the verticaloutput driver 116 (and/or a bus) in a manner that mitigates substratecurrent. Pursuant to another example, the pre-charger 118 can be adistributed device that provides increased width to enable handlingpre-charge of the entire pixel array 102.

Moreover, the booster 120 can further increase the high voltage level ordecrease the low voltage level yielded by the pre-charger 118 to reach atarget voltage level at a given time. Thus, the booster 120 can providepositive boosting whereby the voltage is raised above the high voltagelevel to the target voltage level. Further, the booster 120 can yieldnegative boosting where the voltage is lowered below the low voltagelevel to the target voltage level. Positive boosting can be employed forthe transfer signal and the reset signal, while negative boosting can beutilized for the transfer signal only.

The booster 120 can have variable drive capability; thus, operation ofthe booster 120 can vary according to various degrees of freedom (e.g.,speed of the booster 120 proceeding to a target voltage, frequency ofyielding charge to a boosted node, target voltage, timing of the booster120 along with timing of disparate components such as the pre-charger118, . . . ). For instance, a step size employed by the booster 120 canbe adjustable based upon a number of capacitors utilized. Further, aspeed of the booster 120 can be adjustable as a function of biascurrent; thus, the booster 120 can be sped up by increasing the biascurrent or slowed down by decreasing the bias current. Additionally, thebooster 120 can be disabled with timing to save power and/or noise whenthe booster 120 is not being used. Moreover, the booster 120 can includea comparator to disable the booster 120 when the target voltage level isreached, which can provide consistent boosting voltage to all (orsubstantially all) rows of the pixel array 102. In contrast,conventional techniques that provide non-uniform boosting can lead toFixed Pattern Noise (FPN) or row noise issues.

According to an illustration, the vertical output driver 116 can quicklytransition from yielding an output with a voltage below Ground (e.g.,V_Boost negative) to yielding an output with a voltage above Vdd (e.g.,the output voltage provided by the vertical output driver 116 upon a buscan be V_Boost positive, which is greater than Vdd). Upon switching, thepre-charger 118 can quickly raise the voltage of the output to Vdd fromV_Boost negative. The pre-charger 118, rather than the booster 120, canbe utilized to increase the voltage of the output initially, since thebooster 120 may be unable to supply sufficient current during switching(e.g., global switching, . . . ). After this initial voltage increase,the pre-charger 118 can be turned to an off state and the booster 120can be employed to further raise the voltage from Vdd to V_Boostpositive. For instance, the booster 120 can be transitioned from an offstate to an on state to raise the voltage from Vdd to V_Boost positive;this can enable conserving power and/or mitigating noise. Alternatively,the booster 120 can be in the on state while the pre-charger 118 raisesthe voltage to Vdd, and thus, the booster 120 can remain in the on stateafter the pre-charger 118 switches to the off state. Moreover, thesystem 100 can similarly transition the outputted voltage to a voltagelevel boosted below a low voltage level (e.g., to V_Boost negative).Further, it is to be appreciated that the claimed subject matter is notlimited to the aforementioned illustration, as transitioning betweenoutputted voltage levels can start at any voltage level, proceed to anyintermediate voltage level at which the pre-charger 118 is disengaged,and/or continue to any boosted voltage level.

Utilization of the system 100 addresses various challenges commonlyencountered by conventional boosting techniques when employing globalshutter operation and/or rolling shutter operation. For instance, forglobal shutter mode, the system 100 enhances speed of the booster 120,allows transfer gate voltage to range from above Vdd to below Ground(e.g., 5.0 V to −2.0 V, . . . ), prevents substrate current fromflowing, and controls timing of the booster 120. According to a furtherexample, for rolling shutter mode, the system 100 enhances speed andpower of the booster 120, controls step size yielded by the booster 120to provide uniform operation for all rows of the pixel array 102,enhances long term device reliability for transistors connected toboosted nodes, and controls timing, rise and fall times, etc. of thebooster 120. It is to be appreciated, however, that the claimed subjectmatter is not limited to the aforementioned.

Now turning to FIG. 2, illustrated is an example CMOS imager pixel cell200 that can be included in a pixel array (e.g., the pixel array 102 ofFIG. 1). The pixel cell 200 includes a photodiode 202 connected to atransfer transistor 204. The transfer transistor 204 is furtherconnected to a floating diffusion region 206. The floating diffusionregion 206 connects to a source follower transistor 208 and a resettransistor 210. The source follower transistor 208 is further connectedto a select transistor 212. The select transistor 212 can be employed toselect a particular row of pixel cells from a pixel array.

The photodiode 202 can be charged by converting optical energy toelectrical energy. For instance, the photodiode 202 can have sensitivityto a particular type of incident light (e.g., red light, blue light,green light). Moreover, the type of light to which the photodiode 202 issensitive can indicate a type of the pixel cell 200 (e.g., R pixel, Bpixel, G pixel). Light can be integrated at the photodiode 202 andelectrons generated from the light can be transferred to the floatingdiffusion region 206 (e.g., in a noiseless or substantially noiselessmanner) when a transfer signal (TX) is received at a gate of thetransfer transistor 204. Thus, until reception of the TX, the light canbe integrated.

According to an illustration, the floating diffusion region 206 can bereset to a known state before transfer of charge thereto. Resetting ofthe floating diffusion region 206 can be effectuated by the resettransistor 210. The reset transistor 210 can reset the floatingdiffusion region 206 to a reset voltage provided by a reset bus uponreceiving a reset signal at the gate of the reset transistor 210.Further, the transfer transistor 204 can transfer charge (e.g., yieldedby the photodiode 202) to the floating diffusion region 206. The chargecan be transferred in response to a transfer signal (TX) received at agate of the transfer transistor 204. Moreover, the pixel cell 200 (alongwith other pixel cell(s) in the same row of the pixel array) can beselected for readout by employing the select transistor 212. Readout canbe effectuated via a read bus 214 (e.g., one of the read buses 104 ofFIG. 1). Further, the source follower transistor 208 can output and/oramplify a signal representing a reset voltage (e.g., provided via areset bus) and a pixel signal voltage based on the photo convertedcharges.

The transfer signal and the reset signal can be boosted signals. Moreparticularly, the transfer signal can be positively boosted above a highvoltage level (e.g. boosted above Vdd to V_Boost positive, . . . ) andnegatively boosted below a low voltage level (e.g., boosted below Groundto V_Boost negative, . . . ), while the reset signal can be positivelyboosted above a high voltage level (e.g., boosted above Vdd to V_Boostpositive, . . . ).

The reset signal can be positively boosted to enable resetting thefloating diffusion region 206 to a highest possible voltage (e.g., resetvoltage, voltage approaching or equal to Vdd, . . . ). The chargecollected by the photodiode 202 can thereafter be transferred via thetransfer transistor 204 to the floating diffusion region 206, where thischarge decreases the voltage at the floating diffusion region 206. Thus,increasing the reset voltage level of the floating diffusion region 206can maximize a range over which the floating diffusion region 206operates. According to a further illustration, the reset transistor 210can be a NMOS transistor. Following this illustration, a source of thereset transistor 210 can be connected to the reset bus, which can be ata voltage equal to Vdd. A drain of the reset transistor 210 can beconnected to the floating diffusion region 206. Thus, to enable thefloating diffusion region 206 to go to Vdd, the gate of the resettransistor 210 can be overdriven by at least a threshold voltage (Vt).Hence, the reset signal can be equal to at least Vdd+Vt. For example,Vdd can be 3.3 V and Vt can be 1.0 V, and therefore, the reset signalcan be positively boosted to at least 4.3 V (e.g., pre-charged to 3.3 Vand then positively boosted from 3.3 V to 4.3 V, . . . ); however, it isto be appreciated that the claimed subject matter is not so limitedsince any voltage can be utilized for Vdd and/or Vt.

Further, the transfer signal can be negatively boosted (e.g., belowGround) to mitigate dark current at the transfer transistor 204, whichreduces charge transference from the output of the photodiode 202 to thefloating diffusion region 206 while the transfer transistor 204 is in anoff state. For instance, when the transfer signal is more negative, thetransfer transistor 204 turns more to the off state. According to anexample, the transfer signal can be negatively boosted to −2.0 V (e.g.,pre-charged to Ground and then negatively boosted from Ground to −2.0 V,. . . ); however, the claimed subject matter is not so limited. Yet, thesubstrate typically is to be most negative; thus, a triple well can beutilized to create isolation between the circuits driving the transfertransistor 204 and the substrate.

Moreover, the transfer signal can be positively boosted (e.g., aboveVdd) to reduce lag, which can result when charge fails to be fullytransferred from the output of the photodiode 202 to the floatingdiffusion region 206. To mitigate charge yielded by the photodiode 202from failing to be transferred to the floating diffusion region 206, thetransfer transistor 204 can be provided a transfer signal that isoverdriven above a high voltage level (e.g., boosted above Vdd toV_Boost-positive), which can lower the potential barrier between the twosides of the gate of the transfer transistor 204 to enhance flowing ofthe charge. For example, the transfer signal can be boosted by 0.5 V,1.0 V, etc. above Vdd; however, the claimed subject matter is not solimited. In contrast, conventional techniques that fail to boost thevoltage level of the transfer signal can yield incomplete transfer ofcharge to the floating diffusion region 206. This incomplete transfer,or lag, can result in charge remaining at the output of the photodiode202, which can introduce noise into a subsequent sample.

Now referring to FIG. 3, illustrated is system 300 that positivelyand/or negatively boosts a signal for utilization with a CMOS sensorimager. The system 300 can be a booster such as, for instance, thebooster 120 of FIG. 1. The output from the system 300 can be V_boost,which can be the positively boosted or negatively boosted voltage (e.g.,voltage boosted above Vdd, which can be referred to as V_Boost positive,or voltage boosted below Ground, which can be referred to as V_Boostnegative) provided at an output node (e.g., which can be a bus, . . . ).Moreover, the system 300 can include a voltage-controlled oscillator(VCO) 302, N charge pumps 304 where N can be substantially any integer,a resistor divider 306, a comparator 308, and an AND gate 310.

The VCO 302 can be an electronic oscillator where an oscillationfrequency (e.g., speed, . . . ) of the VCO 302 can be controlled. Forexample, a current (e.g., bias current) inputted to the VCO 302 can setthe speed of the VCO 302, and hence, the speed of the booster (e.g., thesystem 300) in general. Further, the speed of the VCO 302 can be setover a wide range to allow for optimization of speed (e.g., rise/falltime of the booster) and power. According to an illustration, thefrequency of the VCO 302 can range to 400 MHz; however, it is to beappreciated that the claimed subject matter is not so limited. The VCO302 can output clock signals (CLK), which can be inputted to the Ncharge pumps 304. Hence, the frequency to which the VCO 302 is set candetermine a frequency of an occurrence of charge transfer from thebooster to a node (e.g., bus, . . . ) connected to the pixel array.

The system 300 can include N charge pumps 304, and it is to beappreciated that N can be substantially any integer. Further, the numberof charge pumps 304 utilized at a given time is not fixed. Thus, asubset or all of the N charge pumps 304 can be activated for operationat a particular time, while a remainder of the N charge pumps 304 can bedeactivated at the particular time. The number of charge pumps 304employed at a given time can be based upon a signal received via anenable bus. This signal can be N-bits wide and can indicate a number ofthe N available charge pumps 304 to enable (e.g., activate) at the giventime. The N charge pumps 304 can be in parallel to each other. Further,the N charge pumps 304 can generate a voltage of V_boost as an output.

According to an illustration, in rolling shutter mode, a small number ofcharge pumps 304 can be used to minimize the step size of the booster. Asmall step size can reduce row-to-row variation of the boosted voltagelevel as the comparator 308 can turn the system 300 off (e.g., viadisabling the VCO 302) at a substantially similar level for all rows.This can minimize a potential for row noise and fixed pattern noise(FPN) issues. A smaller number of active charge pumps 304 can alsoreduce power supply spikes (e.g., noise, . . . ).

By way of another example, in global shutter mode, the load of thebooster (e.g., the load of the system 300) can be an entire pixel array(e.g., the pixel array 102 of FIG. 1); for instance, the load of theentire pixel array can be on the order of a few nF to a few 10's of nF(e.g., 12 million pixels in the pixel array can be associated with aload around 50 nF, . . . ). Thus, a large number of charge pumps 304 canbe activated and utilized to maximize the speed of the booster duringglobal shutter operations. For global boosting operations, the step sizecan automatically be small since the load capacitance can be much larger(e.g., 100-1000 times larger) when associated with the entire arrayrather than a single row.

The resistor divider 306 can include two resistors. Further, theseresistors can provide large resistances to limit current; however, theclaimed subject matter is not so limited. The resistor divider 306 isused to feedback the boost voltage (e.g., V_boost) to the comparator308. This feedback voltage can be referred to as V_feedback, which canbe the boost voltage times a ratio of resistances from the resistordivider 306.

The comparator 308 is a device that compares two voltages and switchesits output to indicate which is larger. More particularly, thecomparator 308 compares V_feedback to a reference voltage (e.g., V_ref).The comparator 308 output can be switched to a low state, which disablesthe VCO 302, when the feedback voltage is greater than the referencevoltage (e.g., V_feedback is larger than V_ref) when raising the voltageto V_Boost positive. Further, the output from the comparator 308 can beswitched to a high state to enable the VCO 302 upon the referencevoltage being greater than the feedback voltage. According to anotherillustration, when lowering the voltage to V_Boost negative, thecomparator 308 output from the comparator 308 can be switched to a lowstate to disable VCO 302 upon the feedback voltage being less than thereference voltage (e.g., V_feedback is less than V_ref). Additionally,when lowering the voltage to V_Boost negative, the output from thecomparator 308 can be in a high state to enable the VCO 302 upon thereference voltage being less than the feedback voltage. Moreover, thereference voltage (e.g., V_ref) can be adjustable (e.g., using a digitalto analog converter (DAC), . . . ) to achieve an adjustable V_boostvoltage.

Moreover, the comparator 308 can be coupled to the AND gate 310. The ANDgate 310 can yield a high state output when both inputs to the AND gate310 are in high states. Thus, when the comparator 308 yields a highstate output (e.g., when the reference voltage is greater than thefeedback voltage) and a boost enable signal (e.g., Boost_en) inputted tothe AND gate 310 is in a high state, the AND gate 310 can yield anoutput that activates the VCO 302. Otherwise, if either or both of theinputs to the AND gate 310 are in a low state, the AND gate 310 inhibitsoperation of the VCO 302 (e.g., as well as the system 300 in general).Thus, Boost_en controls when the booster (e.g., the system 300) is in anon state. For instance, Boost_en allows for controllability of whenduring a line and/or frame the charge pump(s) 304 are active. This canbe useful in saving power and reducing noise. Also, the exposure ofdevices connected to the boosted voltage levels can be minimized tomaximize device reliability.

Now referring to FIG. 4, illustrated is a system 400 that generatesoutput signals provided to gates of transfer transistors and/or resettransistors of pixels in a pixel array of a CMOS sensor imager. Thesystem 400 is an example of an output stage of a vertical scanner thatallows for output voltages above and below the normal supply levels. Forinstance, there can be an output stage similar to the system 400 foreach row in a pixel array (e.g., the pixel array 102 of FIG. 1) and foreach signal in each row that is to be driven with levels outside thesupply range of Ground to Vdd. Further, the system 400 can be thevertical output driver 116 and pre-charger 118 of FIG. 1.

The system 400 includes a Vhigh bus 402 and a Vlow bus 404, which arebuses that run the length of the vertical scanner and are shared for allrows in the vertical scanner. A high pre-charge circuit 406 (e.g., thepre-charger 118 of FIG. 1, . . . ) can be coupled to the Vhigh bus 402,while a low pre-charge circuit 408 (e.g., the pre-charger 118 of FIG. 1,. . . ) can be coupled to the Vlow bus 404. The high pre-charge circuit406 can include two PMOS transistors (e.g., PMOS transistor 410 and PMOStransistor 412) while the low pre-charge circuit 408 can include twoNMOS transistors (e.g., NMOS transistor 414 and NMOS transistor 416).Further, the Vhigh bus 402 can be coupled to a PMOS transistor 418 andthe Vlow bus 404 can be coupled to an NMOS transistor 420. Moreover, theNMOS transistors 414, 416, 420 can be triple well devices to enablelowering a voltage upon the Vlow bus 404 below Ground (e.g., lower than−0.7 V, . . . ). Additionally, device reliability for transistorsconnected to boosted nodes can be improved by increasing device lengthand minimizing the exposure (e.g., duty cycle) of the devices to voltagelevels outside of the normal supply range.

The high pre-charge circuit 406 can bring the Vhigh bus 402 to a levelof Vdd volts. For instance, when booster speed and/or current areinadequate (e.g., when employing global shutter operation), a pre-chargehigh signal can be used to initially bring the Vhigh bus 402 to a levelof Vdd volts (e.g., VDDA, . . . ). Accordingly, a booster (e.g., thebooster 120 of FIG. 1, the system 300 of FIG. 3, can begin boosting fromVdd volts instead of from V_Boost_negative volts, which allows thebooster to reach a positive target voltage level (e.g.,V_Boost_positive) faster since it starts from a voltage level closer tothe positive target voltage level.

Utilization of the high pre-charge circuit 406 to pre-charge the Vhighbus 402 can be employed for global shutter operation; however, it isalso contemplated that pre-charging can be employed when using rollingshutter mode. As such, this pre-charging can provide power to a positivebooster level shifter 422 during switching. In contrast, withoutpre-charging, the Vhigh bus 402 can collapse when global switching isattempted since the booster may not be able to provide the currentnecessary to switch the entire array at the same time.

The low pre-charge circuit 408 can bring the Vlow bus 404 to a level ofGround volts. For example, when booster speed is inadequate (e.g., whenemploying global shutter operation), a pre-charge low signal can beutilized to initially bring the Vlow bus 404 to a level of Ground volts(e.g., GNDA, . . . ). Hence, the booster can initiate boosting fromGround volts instead of from V_Boost_positive volts, which allows thebooster to reach a negative target voltage level (e.g., V_Boostnegative) faster since it starts from a voltage level closer to thenegative target voltage level.

The low pre-charge circuit 408 can be employed to pre-charge the Vlowbus 404 during global shutter operation; yet, it is also contemplatedthat pre-charging can be used for rolling shutter operation. Thispre-charging can provide power to a negative booster level shifter 424during switching. On the contrary, without pre-charging, the Vlow bus404 can collapse when global switching is attempted since the boostermay not be able to provide the current necessary to switch the entirearray at the same time.

The input to the positive booster level shifter 422 and the negativebooster level shifter 424 is a SIG_OFF signal. When the SIG_OFF signalis at a high state, the output can go to a low state, and vice versa.Further, the positive booster level shifter 422 can be a level shifterpowered from V_Boost_positive so that output high level can equalV_Boost positive and Ground. Accordingly, this can turn off the PMOSswitch (e.g., the PMOS transistor 418) that controls the output.Moreover, the negative booster level shifter 424 can be a level shifterpowered from V_Boost negative and Vdd so that the output low level canequal V_Boost_positive. Hence, this can be utilized to turn off the NMOSswitch (e.g., the NMOS transistor 420) that controls the output.

Moreover, it is to be appreciated that it may not be necessary to havepre-charge switches in each row; rather, a switch that can conductcurrent for the pre-charging of the entire pixel array during globaloperation can be utilized. This current can be on the order of hundredsof milliamps to a few amps for the switching transient, for example.According to another illustration, instead of having one very largetransistor, it can be convenient to have a small pre-charge switch inevery row, or in every few rows, to achieve the final size needed.

Additionally, the high pre-charge circuit 406 and the low pre-chargecircuit 408 can each have body connections to mitigate current flowthrough bodies of devices under various conditions. For instance, thehigh pre-charge circuit 406 can employ body connections that mitigatecurrent flowing through the bodies of the devices if Vhigh falls belowVdd. Moreover, the low pre-charge circuit 408 can utilize bodyconnections that mitigate current flowing through the bodies of thedevices if Vlow rises above Ground.

Now turning to FIG. 5, illustrated are example diagrams depicting bodyconnections of pre-charge devices. Either pre-charge device 500 orpre-charge device 502 can be the high pre-charge circuit 406 of FIG. 4;the pre-charge device 500 and the pre-charge device 502 can each includethe PMOS transistors 410 and 412. Similarly, pre-charge device 504 orpre-charge device 506 can be the low pre-charge circuit 408 of FIG. 4,where the pre-charge device 504 and the pre-charge device 506 can eachinclude the NMOS transistors 414 and 416. By way of illustration,implications of body connections utilized in the pre-charge device 500are contrasted with implications of body connections employed for thepre-charge device 502, and implications of body connections used withthe pre-charge device 504 are compared to implications of bodyconnections leveraged by the pre-charge device 506. However, it is to beappreciated that the claimed subject matter is not limited to thedepicted examples.

Body connections of the pre-charge device 500 can result in largeamounts of well current flow, which can be undesirable. Moreparticularly, if Vhigh, which is the n-well potential, goes below Vdd, adiode 508 between Vdd and the well formed by the source of the PMOS willturn on causing large amounts of well current to flow. This can damagethe device and is undesirable since when the pre-charge device 500 is inthe off (e.g., high) state, no connection should exist between Vdd andVhigh. In contrast, the pre-charge device 502 can isolate Vdd and Vhighwhen the pre-charge device 502 is in the off (e.g., high) state. For thepre-charge device 502, if Vhigh goes below Vdd, no substrate current canflow since the n-wells of the two PMOS transistors 410 and 412 areisolated (e.g., as shown at 512 in contrast to a connection 510 betweenthe n-wells of the PMOS transistors 410 and 412 in the pre-charge device500). Thus, risk of device damage due to well current flow when thepre-charge device 502 is in the off state can be mitigated. Accordingly,the pre-charge device 502 can be utilized in connection with the system400 of FIG. 4 (e.g., rather than the pre-charge device 500).

Moreover, pre-charge device 506 can be employed in connection with thesystem 400 of FIG. 4 instead of the pre-charge device 504. For instance,with the pre-charge device 504, if Vlow, which is the p-well potential,goes above Ground, a diode 514 between Ground and the well (e.g., Vlow)formed by the source of the triple well NMOS can turn on causing largeamounts of well current to flow. This can damage the device and isundesirable since when the pre-charge device 504 is in the off (e.g.,low) state, no connection should exist between Ground and Vlow. On thecontrary, the pre-charge device 506 can isolate Ground and Vlow when thepre-charge device 506 is in the off (e.g., low) state. For thepre-charge device 506, if Vlow goes above Ground, no substrate currentcan flow since the p-wells of the two NMOS transistors 414 and 416 areisolated (e.g., as shown at 518 in contrast to a connection 516 betweenthe p-wells of the NMOS transistors 414 and 416 in the pre-charge device504). Hence, risk of device damage resulting from well current flow whenthe pre-charge device 506 is in the off state can be mitigated, andthus, the pre-charge device 506 can be leveraged in connection with thesystem 400 of FIG. 4 (e.g., rather than the pre-charge device 504).

Now referring to FIG. 6, illustrated is a system 600 that controlsvoltage boosting in a CMOS sensor imager. The system 600 includes thevertical output driver 116 that can yield a signal upon a bus that canbe provided to pixels in a pixel array (e.g., the pixel array 102 ofFIG. 1). Further, the system 600 includes the high pre-charge circuit406, the low pre-charge circuit 408, and the booster 120 as describedherein. Moreover, the system 600 includes a control component 602 thatcan control operation of the vertical output driver 116, the highpre-charge circuit 406, the low pre-charge circuit 408, and/or thebooster 120. For instance, the control component 602 can coordinateoperations effectuated by the vertical output driver 116, the highpre-charge circuit 406, the low pre-charge circuit 408, and/or thebooster 120.

According to an illustration, the control component 602 can be a readstate machine that yields signals to transition between on and offstates. For instance, the control component 602 can include a patterngenerator (not shown) that initiates transfer of these signals via apattern. The pattern can be predefined (e.g., the pattern can beretained in memory and/or instructions to generate the pattern can beretained in memory), generated based upon feedback, initialized by auser, and so forth. As an example of a signal that can be yielded, thecontrol component 602 can provide a Boost_en signal to the booster 120that switches the booster 120 on or off. Thus, the control component candisable and enable the booster 120 based upon timing communicated viathe Boost_en signal. Further, the control component 602 can provide apre-charge high signal to the high pre-charge circuit 406 and/or apre-charge low signal to the low pre-charge circuit 408 to change on/offstates of the high pre-charge circuit 406 and the low pre-charge circuit408, respectively. Moreover, the control component 602 can output aSIG_OFF signal for the vertical output driver 116 as described herein.It is to be appreciated that the forgoing signals yielded by the controlcomponent 602 are provided for illustration purposes, and the claimedsubject matter is not so limited since the control component 602 cancoordinate operation of the system 600 via generating any disparatesignal(s) in addition to or instead of the aforementioned examples.

Pursuant to a further example, the control component 602 can controloperation of the booster 120. For instance, the control component 602can control a number of charge pumps (e.g., the charge pumps 304 of FIG.3) to activate for yielding a boosted voltage (e.g., via sending asignal via an enable bus to the booster 120) at a given time. Thus, theamount of charge dumped upon a boosted node (e.g., bus) per clock cyclecan be controlled (e.g., more charge pumps can yield more charge percycle, less charge pumps can generate less charge per cycle, Followingthis example, the control component 602 can evaluate a performancemetric to alter the number of activated charge pumps out of a set ofavailable charge pumps. Moreover, the control component 602 can controlthe frequency of a VCO (e.g., the VCO 302 of FIG. 3) via adjusting thecurrent inputted to the VCO of the booster 120. Changing the frequencyof the VCO can managed the frequency of how often charge is dumped ontothe boosted node. According to another illustration, the controlcomponent 602 can manipulate a value of a reference voltage (e.g.,V_ref) utilized by the booster 120. The reference voltage can becompared (e.g., via the comparator 308 of FIG. 3) to feedback voltage(e.g., V_feedback), where the feedback voltage can be outputted from aresistor divider (e.g., the resistor divider 306 of FIG. 3) that has theboosted voltage (e.g., V_Boost) as its input. Further, the controlcomponent 602 can control timing of the booster 120 (as well as timingassociated with the system 600 in general). In contrast, conventionalboosters oftentimes provide crude control capabilities such as beingable to adjust an initial voltage level without being able to handlevoltage level decay, variation in voltage level, and the like, which thebooster 120 can enable.

Further, the control component 602 can include and/or be coupled to adata store (not shown). For instance, the data store can retain thepattern utilized by the control component 602 for coordination ofoperations. Further, the data store can retain instructions forgenerating such pattern and/or altering operation of the booster 120; byway of example, the data store can include metrics for evaluatingfeedback associated with the booster 120, which can be utilized by thecontrol component 602 to vary the number of active charge pumps, thespeed of the VCO, the reference voltage, and/or the timing of thebooster 120 (as well as the system 600 in general). Moreover, the datastore can retain instructions for obtaining user input which can beleveraged (e.g., by the control component 602) to control the booster120. The data store can be, for example, either volatile memory ornonvolatile memory, or can include both volatile and nonvolatile memory.By way of illustration, and not limitation, nonvolatile memory caninclude read only memory (ROM), programmable ROM (PROM), electricallyprogrammable ROM (EPROM), electrically erasable programmable ROM(EEPROM), or flash memory. Volatile memory can include random accessmemory (RAM), which acts as external cache memory. By way ofillustration and not limitation, RAM is available in many forms such asstatic RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), doubledata rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM(SLDRAM), Rambus direct RAM (RDRAM), direct Rambus dynamic RAM (DRDRAM),and Rambus dynamic RAM (RDRAM). The data store of the subject systemsand methods is intended to comprise, without being limited to, these andany other suitable types of memory. In addition, it is to be appreciatedthat the data store can be a server, a database, a hard drive, and thelike.

FIGS. 7-8 illustrate methodologies in accordance with the claimedsubject matter. For simplicity of explanation, the methodologies aredepicted and described as a series of acts. It is to be understood andappreciated that the subject innovation is not limited by the actsillustrated and/or by the order of acts, for example acts can occur invarious orders and/or concurrently, and with other acts not presentedand described herein. Furthermore, not all illustrated acts may berequired to implement the methodologies in accordance with the claimedsubject matter. In addition, those skilled in the art will understandand appreciate that the methodologies could alternatively be representedas a series of interrelated states via a state diagram or events.

With reference to FIG. 7, illustrated is a methodology 700 thatfacilitates reducing lag and dark current in a CMOS sensor imager. At702, a bus connected to gates of pixels in a pixel array of a CMOSsensor imager can be pre-charged to a first voltage level. For instance,pre-charging can occur while in global shutter mode or in rollingshutter mode. Further, pre-charging can enable the bus to quicklytransition to a high voltage level (e.g., Vdd) or a low voltage level(e.g., Ground), where the high voltage level or the low voltage levelcan be the first voltage level. According to an illustration, the buscan be pre-charged to switch from the low voltage level (e.g., Ground)or a voltage boosted below the low voltage level (e.g., V_Boostnegative) to the high voltage level (e.g., Vdd). By way of anotherexample, the bus can be pre-charged to switch from the high voltagelevel (e.g., Vdd) or a voltage boosted above the high voltage level(e.g., V_Boost_positive) to the low voltage level (e.g., Ground).Further, the bus can connect to gates of transfer transistors and/orgates of reset transistors of the pixels in the pixel array.

At 704, the bus can be boosted from the first voltage level to a secondvoltage level. For instance, when the first voltage level is the highvoltage level (e.g., Vdd), the bus can be boosted above such highvoltage level to V_Boost_positive. Moreover, when the first voltagelevel is the low voltage level (e.g., Ground), the bus can be boostedbelow such low voltage level to V_Boost negative. Moreover, boosting canoccur subsequent to discontinuation of pre-charging of the bus.

Turning to FIG. 8, illustrated is a methodology 800 that facilitatescontrolling a booster utilized in connection with a CMOS sensor imager.At 802, clock signals can be generated based upon an input current thatcontrols frequency of the clock signals. Further, the clock signals canbe yielded upon receiving a Boost_en signal, while generation of theclock signals can be inhibited when the Boost_en signal is not received.The Boost_en signal, for instance, can be received (e.g., from a readstate machine) subsequent to pre-charging of a boosted output node. At804, charge can be outputted to a boosted output node for each of theclock signals, where the charge can be generated from a selected numberof enabled charge pumps. For instance, N charge pumps can be available,and a subset or all of the N charge pumps can be selected to be enabled(e.g., activated). At 806, a reference voltage can be compared to afeedback voltage, where the feedback voltage can correspond to a voltageat the boosted output node. For instance, the feedback voltage can equala resistance ratio of resistors in a resistor divider times a voltage ofthe boosted output node. Further, the reference voltage can beadjustable (e.g., using a digital to analog converter (DAC)) to adjustthe voltage of the boosted output node. At 808, generation of the clocksignals can be controlled based at least in part upon the comparison.For example, generation of the clock signals can be inhibited when thefeedback voltage is greater than the reference voltage for positiveboosting or when the feedback voltage is less than the reference voltagefor negative boosting.

In order to provide additional context for implementing various aspectsof the claimed subject matter, FIGS. 9-10 and the following discussionis intended to provide a brief, general description of a suitablecomputing environment in which the various aspects of the subjectinnovation may be implemented. For instance, FIGS. 9-10 set forth asuitable computing environment that can interact with the CMOS sensorimagers described herein. According to an example, output yielded by theCMOS sensor imagers described above can be obtained and/or furtheroperated upon via employing the following exemplary computingenvironment and/or operation of boosters used with the CMOS sensorimagers can be controlled via using the following exemplary computingenvironment. However, it is to be appreciated that the claimed subjectmatter need not be employed in connection with the computing environmentdescribed below.

While the claimed subject matter has been described above in the generalcontext of computer-executable instructions of a computer program thatruns on a local computer and/or remote computer, those skilled in theart will recognize that the subject innovation also may be implementedin combination with other program modules. Generally, program modulesinclude routines, programs, components, data structures, etc., thatperform particular tasks and/or implement particular abstract datatypes.

Moreover, those skilled in the art will appreciate that the inventivemethods may be practiced with other computer system configurations,including single-processor or multi-processor computer systems,minicomputers, mainframe computers, as well as personal computers,hand-held computing devices, microprocessor-based and/or programmableconsumer electronics, and the like, each of which may operativelycommunicate with one or more associated devices. The illustrated aspectsof the claimed subject matter may also be practiced in distributedcomputing environments where certain tasks are performed by remoteprocessing devices that are linked through a communications network.However, some, if not all, aspects of the subject innovation may bepracticed on stand-alone computers. In a distributed computingenvironment, program modules may be located in local and/or remotememory storage devices.

FIG. 9 is a schematic block diagram of a sample-computing environment900 with which the claimed subject matter can interact. The system 900includes one or more client(s) 910. The client(s) 910 can be hardwareand/or software (e.g., threads, processes, computing devices). Thesystem 900 also includes one or more server(s) 920. The server(s) 920can be hardware and/or software (e.g., threads, processes, computingdevices). The servers 920 can house threads to perform transformationsby employing the subject innovation, for example.

One possible communication between a client 910 and a server 920 can bein the form of a data packet adapted to be transmitted between two ormore computer processes. The system 900 includes a communicationframework 940 that can be employed to facilitate communications betweenthe client(s) 910 and the server(s) 920. The client(s) 910 are operablyconnected to one or more client data store(s) 950 that can be employedto store information local to the client(s) 910. Similarly, theserver(s) 920 are operably connected to one or more server data store(s)930 that can be employed to store information local to the servers 920.

With reference to FIG. 10, an exemplary environment 1000 forimplementing various aspects of the claimed subject matter includes acomputer 1012. The computer 1012 includes a processing unit 1014, asystem memory 1016, and a system bus 1018. The system bus 1018 couplessystem components including, but not limited to, the system memory 1016to the processing unit 1014. The processing unit 1014 can be any ofvarious available processors. Dual microprocessors and othermultiprocessor architectures also can be employed as the processing unit1014.

The system bus 1018 can be any of several types of bus structure(s)including the memory bus or memory controller, a peripheral bus orexternal bus, and/or a local bus using any variety of available busarchitectures including, but not limited to, Industrial StandardArchitecture (ISA), Micro-Channel Architecture (MSA), Extended ISA(EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB),Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus(USB), Advanced Graphics Port (AGP), Personal Computer Memory CardInternational Association bus (PCMCIA), Firewire (IEEE 1394), and SmallComputer Systems Interface (SCSI).

The system memory 1016 includes volatile memory 1020 and nonvolatilememory 1022. The basic input/output system (BIOS), containing the basicroutines to transfer information between elements within the computer1012, such as during start-up, is stored in nonvolatile memory 1022. Byway of illustration, and not limitation, nonvolatile memory 1022 caninclude read only memory (ROM), programmable ROM (PROM), electricallyprogrammable ROM (EPROM), electrically erasable programmable ROM(EEPROM), or flash memory. Volatile memory 1020 includes random accessmemory (RAM), which acts as external cache memory. By way ofillustration and not limitation, RAM is available in many forms such asstatic RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), doubledata rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM(SLDRAM), Rambus direct RAM (RDRAM), direct Rambus dynamic RAM (DRDRAM),and Rambus dynamic RAM (RDRAM).

Computer 1012 also includes removable/non-removable,volatile/non-volatile computer storage media. FIG. 10 illustrates, forexample a disk storage 1024. Disk storage 1024 includes, but is notlimited to, devices like a magnetic disk drive, floppy disk drive, tapedrive, Jaz drive, Zip drive, LS-100 drive, flash memory card, or memorystick. In addition, disk storage 1024 can include storage mediaseparately or in combination with other storage media including, but notlimited to, an optical disk drive such as a compact disk ROM device(CD-ROM), CD recordable drive (CD-R Drive), CD rewritable drive (CD-RWDrive) or a digital versatile disk ROM drive (DVD-ROM). To facilitateconnection of the disk storage devices 1024 to the system bus 1018, aremovable or non-removable interface is typically used such as interface1026.

It is to be appreciated that FIG. 10 describes software that acts as anintermediary between users and the basic computer resources described inthe suitable operating environment 1000. Such software includes anoperating system 1028. Operating system 1028, which can be stored ondisk storage 1024, acts to control and allocate resources of thecomputer system 1012. System applications 1030 take advantage of themanagement of resources by operating system 1028 through program modules1032 and program data 1034 stored either in system memory 1016 or ondisk storage 1024. It is to be appreciated that the claimed subjectmatter can be implemented with various operating systems or combinationsof operating systems.

A user enters commands or information into the computer 1012 throughinput device(s) 1036. Input devices 1036 include, but are not limitedto, a pointing device such as a mouse, trackball, stylus, touch pad,keyboard, microphone, joystick, game pad, satellite dish, scanner, TVtuner card, digital camera, digital video camera, web camera, and thelike. These and other input devices connect to the processing unit 1014through the system bus 1018 via interface port(s) 1038. Interfaceport(s) 1038 include, for example, a serial port, a parallel port, agame port, and a universal serial bus (USB). Output device(s) 1040 usesome of the same type of ports as input device(s) 1036. Thus, forexample, a USB port may be used to provide input to computer 1012, andto output information from computer 1012 to an output device 1040.Output adapter 1042 is provided to illustrate that there are some outputdevices 1040 like monitors, speakers, and printers, among other outputdevices 1040, which require special adapters. The output adapters 1042include, by way of illustration and not limitation, video and soundcards that provide a means of connection between the output device 1040and the system bus 1018. It should be noted that other devices and/orsystems of devices provide both input and output capabilities such asremote computer(s) 1044.

Computer 1012 can operate in a networked environment using logicalconnections to one or more remote computers, such as remote computer(s)1044. The remote computer(s) 1044 can be a personal computer, a server,a router, a network PC, a workstation, a microprocessor based appliance,a peer device or other common network node and the like, and typicallyincludes many or all of the elements described relative to computer1012. For purposes of brevity, only a memory storage device 1046 isillustrated with remote computer(s) 1044. Remote computer(s) 1044 islogically connected to computer 1012 through a network interface 1048and then physically connected via communication connection 1050. Networkinterface 1048 encompasses wire and/or wireless communication networkssuch as local-area networks (LAN) and wide-area networks (WAN). LANtechnologies include Fiber Distributed Data Interface (FDDI), CopperDistributed Data Interface (CDDI), Ethernet, Token Ring and the like.WAN technologies include, but are not limited to, point-to-point links,circuit switching networks like Integrated Services Digital Networks(ISDN) and variations thereon, packet switching networks, and DigitalSubscriber Lines (DSL).

Communication connection(s) 1050 refers to the hardware/softwareemployed to connect the network interface 1048 to the bus 1018. Whilecommunication connection 1050 is shown for illustrative clarity insidecomputer 1012, it can also be external to computer 1012. Thehardware/software necessary for connection to the network interface 1048includes, for exemplary purposes only, internal and externaltechnologies such as, modems including regular telephone grade modems,cable modems and DSL modems, ISDN adapters, and Ethernet cards.

What has been described above includes examples of the subjectinnovation. It is, of course, not possible to describe every conceivablecombination of components or methodologies for purposes of describingthe claimed subject matter, but one of ordinary skill in the art mayrecognize that many further combinations and permutations of the subjectinnovation are possible. Accordingly, the claimed subject matter isintended to embrace all such alterations, modifications, and variationsthat fall within the spirit and scope of the appended claims.

In particular and in regard to the various functions performed by theabove described components, devices, circuits, systems and the like, theterms (including a reference to a “means”) used to describe suchcomponents are intended to correspond, unless otherwise indicated, toany component which performs the specified function of the describedcomponent (e.g., a functional equivalent), even though not structurallyequivalent to the disclosed structure, which performs the function inthe herein illustrated exemplary aspects of the claimed subject matter.In this regard, it will also be recognized that the innovation includesa system as well as a computer-readable medium havingcomputer-executable instructions for performing the acts and/or eventsof the various methods of the claimed subject matter.

In addition, while a particular feature of the subject innovation mayhave been disclosed with respect to only one of several implementations,such feature may be combined with one or more other features of theother implementations as may be desired and advantageous for any givenor particular application. Furthermore, to the extent that the terms“includes,” and “including” and variants thereof are used in either thedetailed description or the claims, these terms are intended to beinclusive in a manner similar to the term “comprising.”

1. A system that boosts voltage upon a node connected to pixels in acomplementary metal-oxide-semiconductor (CMOS) imaging system-on-chip(iSoC) sensor, comprising: a vertical output driver that outputs asignal upon a node connected to at least one of gates of resettransistors of pixels in a pixel array or gates of transfer transistorsof pixels in the pixel array; a pre-charger that transitions a voltageof the node to a first voltage level; and a booster with operation thatvaries according to at least one degree of freedom, the booster furtheradjusts the voltage of the node from the first voltage level to a secondvoltage level.
 2. The system of claim 1, the at least one degree offreedom of the booster being at least one of speed of the boosterproceeding to the second voltage level, frequency of yielding charge tothe node, the second voltage level, or timing of the booster and thepre-charger.
 3. The system of claim 1, the booster further comprising: avoltage-controlled oscillator (VCO) that outputs clock signals at afrequency set by an inputted current; a set of charge pumps parallel toeach other, a subset of the set of charge pumps being activated via anenable bus to generate charge outputted upon the node for each of theclock signals; a resistor divider that generates a feedback voltage as afunction of a voltage of the node; a comparator that compares thefeedback voltage to a reference voltage; and an AND gate that enables orinhibits the VCO at a given time based upon output of the comparator anda boost enable signal.
 4. The system of claim 3, the reference voltagebeing adjustable to control the second voltage level to which thebooster adjusts the voltage of the node.
 5. The system of claim 3, astep size of the booster being adjustable based upon a number of chargepumps in the subset that are activated.
 6. The system of claim 3, thefrequency of the booster being adjustable as a function of the inputtedcurrent.
 7. The system of claim 3, the comparator disables the boosterwhen the second voltage level is reached at the node.
 8. The system ofclaim 3, further comprising a control component that disables andenables the booster based upon timing communicated via the boost enablesignal.
 9. The system of claim 1, the pre-charger comprising: a highpre-charge circuit that brings a Vhigh bus included in the verticaloutput driver to a level of Vdd volts upon receiving a pre-charge highsignal; and a low pre-charge circuit that brings a Vlow bus included inthe vertical output driver to a level of Ground volts upon receiving apre-charge low signal.
 10. The system of claim 9, the high pre-chargecircuit initially raises the voltage of the node to Vdd volts and thebooster further raises the voltage of the node to V_Boost positivevolts.
 11. The system of claim 9, the low pre-charge circuit initiallylowers the voltage of the node to Ground volts and the booster furtherlowers the voltage of the node to V_Boost negative volts.
 12. The systemof claim 9, the high pre-charge circuit includes body connections thatisolate the Vhigh bus from Vdd when the high pre-charge circuit is inthe off state to mitigate flowing of substrate current, and the lowpre-charge circuit includes body connections that isolate the Vlow busfrom Ground when the low pre-charge circuit is in the off state tomitigate flowing of substrate current.
 13. The system of claim 1, thepre-charger being a distributed device that provides increased width toenable handling pre-charge of the entire pixel array.
 14. The system ofclaim 1, the pre-charger and the booster operate in a global shuttermode or a rolling shutter mode.
 15. A method that facilitates reducinglag and dark current in a CMOS sensor imager, comprising: pre-charging abus connected to gates of pixels in a pixel array of a CMOS sensorimager to a first voltage level; and boosting the bus from the firstvoltage level to a second voltage level.
 16. The method of claim 15,further comprising controlling the boosting of the bus via at least onedegree of freedom.
 17. The method of claim 16, further comprising:generating clock signals based upon an input current that controlsfrequency of the clock signals; outputting charge to the bus for each ofthe clock signals, the charge being generated from a selected number ofenabled charge pumps; comparing a reference voltage to a feedbackvoltage, the feedback voltage corresponds to a voltage at the bus; andcontrolling generation of the clock signals based at least in part uponthe comparison.
 18. The method of claim 15, further comprisingpre-charging the bus while in global shutter mode or in rolling shuttermode.
 19. The method of claim 15, further comprising boosting the bussubsequent to discontinuation of pre-charging the bus.
 20. A system thatenables controlling a booster utilized in a CMOS sensor imager,comprising: means for generating clock signals based upon an adjustableinput bias current that controls frequency of the clock signals; meansfor outputting charge to a boosted output node for each of the clocksignals, the charge being generated from a selected number of activatedcharge pumps based upon a signal obtained via an enable bus; means fordetermining a feedback voltage based upon a voltage at the boostedoutput node; means for comparing an adjustable reference voltage to thefeedback voltage; and means for controlling generation of the clocksignals based upon the comparison and a received boost enable signal.